I / O and Memory Interfacing Features and Benefits in 7 Series Architecture

www.xilinx.com 1 © Copyright 2011–2012 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. The input and output (I/O) functionality in any FPGA needs to be designed to address a wide array of applications of varied performance and function. The I/O in the 7 series FPGAs and ZynqTM-7000 All Programmable SoCs (AP SoCs) from Xilinx have been optimized for a diverse set of requirements at both the physical and logical level, including high-speed memory, networking, video flat panel and sensor interfaces, high-speed ADC/DACs connectivity as well as legacy interfaces. Additionally, new hard blocks have been added specifically to benefit memory interfacing for high-speed DDR3 devices.